struct _MI_HARDWARE_STATE// Size=0x78
{
    unsigned long NodeMask;// Offset=0x0 Size=0x4
    unsigned short * NodeGraph;// Offset=0x4 Size=0x4
    struct _MI_SYSTEM_NODE_INFORMATION * SystemNodeInformation;// Offset=0x8 Size=0x4
    unsigned long NumaLastRangeIndex;// Offset=0xc Size=0x4
    struct _HAL_NODE_RANGE * NumaMemoryRanges;// Offset=0x10 Size=0x4
    unsigned char NumaTableCaptured;// Offset=0x14 Size=0x1
    unsigned char NodeShift;// Offset=0x15 Size=0x1
    struct _HAL_CHANNEL_MEMORY_RANGES * ChannelMemoryRanges;// Offset=0x18 Size=0x4
    unsigned char ChannelShift;// Offset=0x1c Size=0x1
    unsigned long SecondLevelCacheSize;// Offset=0x20 Size=0x4
    unsigned long FirstLevelCacheSize;// Offset=0x24 Size=0x4
    unsigned long PhysicalAddressBits;// Offset=0x28 Size=0x4
    unsigned char WriteCombiningPtes;// Offset=0x2c Size=0x1
    unsigned char AllMainMemoryMustBeCached;// Offset=0x2d Size=0x1
    unsigned long TotalPagesAllowed;// Offset=0x30 Size=0x4
    unsigned long SecondaryColorMask;// Offset=0x34 Size=0x4
    unsigned long SecondaryColors;// Offset=0x38 Size=0x4
    unsigned long FlushTbForAttributeChange;// Offset=0x3c Size=0x4
    unsigned long FlushCacheForAttributeChange;// Offset=0x40 Size=0x4
    unsigned long FlushCacheForPageAttributeChange;// Offset=0x44 Size=0x4
    unsigned long CacheFlushPromoteThreshold;// Offset=0x48 Size=0x4
    unsigned long FlushTbThreshold;// Offset=0x4c Size=0x4
    struct _MI_ZERO_COST_COUNTS ZeroCostCounts[2];// Offset=0x50 Size=0x20
    unsigned long HighestPossiblePhysicalPage;// Offset=0x70 Size=0x4
};